When TSMC released its third-quarter 2026 earnings on October 15, the headline numbers were staggering: $46.72 billion in revenue, up 41.2% year-over-year; net profit up 69% to an all-time record; fourth-quarter guidance projecting a 58% year-over-year surge. Analysts reached for superlatives. Investors immediately asked: if demand is this strong, why can’t TSMC make more chips?
The answer reveals one of the most consequential supply constraints in modern technology history — a crunch that affects every company building AI products and every consumer who uses them.
Six Straight Record Quarters, and the Ceiling Isn’t in Sight
TSMC’s Q3 2026 results mark its sixth consecutive record quarter. The company’s Taiwan fabs are running near theoretical maximum utilization. Its advanced packaging technology — a manufacturing process called CoWoS (Chip-on-Wafer-on-Substrate) that stacks multiple processor dies together into the dense, power-efficient packages that power today’s AI accelerators — is effectively sold out through at least mid-2027.
“Demand continues to far exceed our ability to supply,” TSMC CEO C.C. Wei told analysts on the October 15 earnings call. “Every customer is asking for more than we can allocate to them.”
That customer list includes the most powerful technology companies on earth, and right now they are all competing for the same scarce manufacturing slots.
The Capacity Battle: Who Gets the Wafers
According to analysis from Morgan Stanley and capacity tracking firm Silicon Analysts, Nvidia currently holds approximately 60% of TSMC’s total CoWoS advanced packaging allocation — a dominant position it has secured through long-term supply commitments and aggressive pre-booking going back to 2024. The remaining 40% is split among Apple (for the M-series and custom silicon in its AI devices), Broadcom (which designs the AI accelerators used by Google and Meta), AMD, and a growing list of hyperscaler custom silicon programs from Amazon, Microsoft, and Google.
The squeeze is not hypothetical. Multiple hyperscalers have privately acknowledged to suppliers that their AI infrastructure buildout timelines are running 6 to 12 months behind original projections — not because of software, not because of power, but because the chips aren’t ready when needed. A cloud provider that planned to deploy a new AI training cluster in Q2 2026 may now be looking at Q4 2026 or Q1 2027.
For enterprises buying commercial AI services, this bottleneck is largely invisible. It shows up instead in pricing: cloud AI inference costs have declined more slowly than expected because providers cannot add capacity as quickly as demand grows.
The 2nm Problem
The competition for capacity is about to intensify further. TSMC’s N2 (2-nanometer) process node — the most advanced manufacturing technology the company has ever produced, and the node on which Nvidia’s next generation of AI accelerators will be built — is already almost fully booked for the next two years. TSMC is ramping N2 production toward 100,000 wafers per month by the end of 2026, but even at that volume, demand is projected to outstrip supply well into 2028.
Brokerage analysts tracking TSMC’s capital expenditure plans now forecast the company will need to spend roughly $105 billion in 2028 alone to stay ahead of demand — a figure that would have seemed fantastical just three years ago. For context, TSMC’s total capex for all of 2023 was approximately $32 billion.
The N2 node matters for a specific technical reason: it enables AI accelerator designs that consume substantially less power per computation than the previous generation. For hyperscalers running data centers that consume hundreds of megawatts, moving from N3 to N2 chips could reduce cooling and power costs by 30 to 40% per unit of AI compute. Every major AI infrastructure operator wants those chips as soon as they exist. The problem is that “as soon as they exist” and “in the quantities we need” are two very different things.
Arizona and the Limits of Geographic Diversification
TSMC’s answer to both the supply crunch and geopolitical pressure from Washington is its Arizona expansion program. The company has committed to building four fabs in Phoenix, with total planned investment now raised to $265 billion — the largest foreign direct investment in American manufacturing history. The Arizona fabs are designed to produce N3 and eventually N2 chips, giving US customers a domestic supply option that doesn’t depend on Taiwan being geologically and politically stable.
But Arizona is not a near-term fix. The first Arizona fab only began volume production in late 2025, and yields — the percentage of chips that come off the line working correctly — are still ramping toward the efficiency levels of TSMC’s Taiwan operations. Building and ramping a semiconductor fab is a process that takes years, not quarters. Even with aggressive investment, Arizona’s total contribution to global advanced chip capacity in 2026 is estimated at less than 10%.
What This Means for Samsung and Intel
The capacity crunch has created an opening that Samsung and Intel’s foundry businesses are working hard to exploit. Both companies have been investing heavily in their own advanced packaging technologies and manufacturing processes, positioning themselves as overflow suppliers for customers that can’t get allocation from TSMC.
Samsung’s Gate-All-Around (GAA) process has shown improved yield progress in 2026, and it has signed packaging agreements with several AI chip design companies that were unable to secure TSMC slots. Intel Foundry, after a turbulent 2025, has attracted early commitments from customers willing to accept slightly lower performance in exchange for guaranteed supply.
The competitive dynamic remains asymmetric: TSMC’s yield rates and process maturity are still significantly ahead of its rivals. Most AI chip designers would prefer TSMC if they could get allocation. But “slightly less optimal than TSMC” is increasingly better than “waiting another 18 months,” and Samsung and Intel are benefiting accordingly.
The Deeper Implication: AI Infrastructure Has a Physical Ceiling
The TSMC capacity story is a reminder that artificial intelligence, for all its software-driven mystique, runs on physical hardware that takes years and billions of dollars to build. The exponential growth curves of AI model capability and AI application adoption sit on top of a supply chain that moves at the speed of fabs, lithography machines, and CoWoS packaging lines.
TSMC’s Q3 2026 results confirm that the company is executing flawlessly — revenue up 41%, profits up 69%, guidance calling for another surge. The constraint isn’t execution. It’s physics. There is a finite amount of advanced manufacturing capacity on earth, it is being consumed faster than it can be expanded, and the allocation of that capacity — who gets the chips, when, and at what price — is increasingly one of the most strategically important questions in technology.
The companies that secure reliable TSMC supply at N2 will have AI infrastructure advantages over their competitors that cannot be quickly erased. The companies that don’t are already placing bets on Samsung, Intel Foundry, and whatever comes next.
Nvidia, Apple, and Broadcom understand this perfectly. That’s why they’re fighting so hard for the same factories.
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