For years, the biggest barrier to practical quantum computing has not been the qubits themselves — it has been keeping them alive long enough to do useful work. Quantum systems are fragile: a stray electromagnetic signal, a temperature fluctuation, even the simple act of measurement can destroy the delicate superpositions that make quantum computation powerful. The solution, quantum error correction, has always required an enormous number of physical qubits to protect every single logical qubit you actually want to use. The overhead was so severe that building a machine with 1,000 useful logical qubits — enough to tackle real-world problems in chemistry, cryptography, and optimization — was projected to require millions of physical qubits and hardware that does not yet exist.
That calculation may have just changed.
On September 15, 2026, Iceberg Quantum and Diraq announced a landmark demonstration: using Iceberg’s Pinnacle quantum low-density parity-check (qLDPC) architecture running on Diraq’s silicon CMOS-based spin-qubit hardware, the two companies achieved a pathway to 1,000 logical qubits using just 150,000 physical qubits. The work was enabled by NVIDIA’s newly announced CUDA-Q Logical layer, a cross-stack platform that allowed the teams to move from abstract logical circuit design all the way down to physical hardware operations on real spin-qubit arrays.
The result is roughly ten times more efficient than Diraq’s previous estimates using conventional surface code error correction — and it challenges a long-standing assumption that advanced qLDPC architectures necessarily demand more complex hardware than simpler approaches.
What Is qLDPC and Why Does It Matter?
To appreciate why this is significant, a brief detour into error correction is necessary. Classical computers protect data by making multiple copies, or by using parity bits — simple checksums that flag when something has gone wrong. Quantum computers cannot copy their states (the no-cloning theorem forbids it), so researchers encode logical qubits across many entangled physical qubits instead.
The most widely used approach, called the surface code, is elegant and relatively forgiving of imperfect hardware. But it is wasteful: protecting a single logical qubit from errors requires hundreds to thousands of physical qubits arranged on a two-dimensional grid. Scaling to 1,000 logical qubits on a surface code architecture could require anywhere from one to ten million physical qubits.
Quantum low-density parity-check codes take a fundamentally different approach. Rather than a flat 2D grid, qLDPC codes use more complex connectivity graphs that allow each physical qubit to participate in checking far more of its neighbors. The upshot is dramatically better overhead: fewer physical qubits per logical qubit, and better protection against errors at the same time. In theory, this is superior in every meaningful way. The practical challenge has always been that implementing the required connectivity is extremely hard on real hardware.
The Pinnacle Architecture
Iceberg Quantum, an Australian startup founded to commercialize advanced fault-tolerant architectures, developed Pinnacle specifically to capture the benefits of qLDPC codes while remaining implementable on realistic quantum hardware. Pinnacle breaks the computation into modular processing blocks where the complex non-local connectivity required by qLDPC codes is only ever needed within each block — never across the whole device. This makes the engineering problem tractable.
The critical question was whether Pinnacle could run on the hardware platforms that are actually being built today, without demanding a level of qubit fidelity or connectivity that does not yet exist.
Silicon Spin Qubits: Small, Dense, and CMOS-Compatible
Diraq, also Australian, builds quantum computers using spin qubits in silicon — the same material that underpins essentially all modern classical computing. Rather than superconducting circuits (which require dilution refrigerators the size of a wardrobe and operate near absolute zero) or trapped ions (which require complex laser systems), Diraq’s spin qubits leverage standard CMOS semiconductor fabrication. Their qubits are defined by the spin states of individual electrons confined in silicon quantum dots, and the chips are manufactured using modified versions of the same industrial processes that produce the processors in your laptop.
This approach has a compelling long-term advantage: integration. If quantum computing is going to scale to millions of qubits, the manufacturing pipeline already exists. The concern, historically, has been whether spin qubits could achieve the fidelities required for advanced error correction. The Iceberg-Diraq collaboration suggests the answer is yes.
The NVIDIA CUDA-Q Logical Layer
The collaboration was made possible by early access to NVIDIA’s CUDA-Q Logical, the newest addition to NVIDIA’s quantum computing platform. CUDA-Q Logical provides a unified software framework for specifying the full compilation stack from logical circuits — the abstract operations your quantum algorithm wants to perform — all the way down to physical qubit operations on a specific hardware architecture.
Practically, this meant that Iceberg Quantum could describe its Pinnacle architecture in terms of logical primitives and then have CUDA-Q Logical compile those down to the physical shuttling and gate operations required on Diraq’s spin-qubit arrays, including shuttling-aware noise simulations that model how qubits accumulate errors as they move through the device.
Sam Stanwyck, Director of Quantum Product at NVIDIA, noted: “Fault-tolerant quantum computing will advance faster when researchers can test new codes and architectures against real hardware constraints before the hardware is built. Using CUDA-Q Logical, Iceberg Quantum and Diraq showed that Pinnacle’s logical advantage carries through to a practical spin-qubit implementation, exactly the kind of rapid co-design needed to turn better ideas into useful quantum systems.”
The Numbers Behind the Headline
The headline figure — 1,000 logical qubits from 150,000 physical qubits — deserves context. That ratio of 150:1 is, by any historical standard, remarkably efficient. Conventional surface code estimates for the same target typically run from 1,000:1 to 10,000:1 or worse depending on the target error rate and the assumed physical gate fidelity. The Pinnacle approach on Diraq’s hardware closes that gap by roughly an order of magnitude.
Equally important, the team verified that physical qubit counts from Iceberg’s theoretical Pinnacle paper agree with hardware-aware estimates on Diraq’s platform to within 5%. This is not a back-of-the-envelope estimate — it is a validated, hardware-realistic projection that accounts for the noise actually present in spin-qubit systems, including the errors that accumulate as qubits are physically shuttled around the array.
“This work demonstrates that we can place the most advanced fault-tolerant error-correction technology on top of our hardware, increasing the projected logical performance of each device by an order of magnitude,” said Andrew Dzurak, CEO and Founder of Diraq. “It means that every improvement in fault tolerance from here has the potential to offer an improvement in what our devices can do.”
Why This Changes the Roadmap
The implications reach beyond the two companies involved. The quantum computing industry has been wrestling with a fundamental question: which hardware platform will get to fault-tolerant, useful scale first? The answer has generally been assumed to favor superconducting qubits (championed by IBM, Google, and others) due to their faster gate speeds and more mature error correction results.
This demonstration does not overturn that assumption overnight. But it does shift the calculus for silicon spin qubits in a meaningful way. If the physical qubit overhead for reaching 1,000 logical qubits is 150,000 rather than millions, the finish line is dramatically closer — and silicon’s manufacturing advantages become far more relevant far sooner.
Future versions of Pinnacle, Iceberg says, will continue to improve the logical efficiency of Diraq’s devices, pushing the overhead even lower. The cross-stack collaboration model that made this possible — hardware specialists, error correction architects, and platform tooling from NVIDIA working in concert — may also become a template for how the rest of the industry accelerates.
The Long Game
Useful fault-tolerant quantum computing is still not here today. The 150,000 physical qubits required for this target do not yet exist on a single Diraq chip, and demonstrating logical qubit operations at scale carries its own engineering challenges distinct from designing the architecture.
But the gap between where the field is and where it needs to be just got measurably smaller. Iceberg Quantum and Diraq have demonstrated that the most advanced error correction architectures can be made to work with the kinds of hardware that can realistically be manufactured at scale — and they have the numbers to prove it.
In a field where progress is often incremental and the finish line seems perpetually distant, that is no small thing.
